Capacitor impedance

Ever since I began designing circuits, I’ve read about bypass capacitor usage.

Engineers make broad statements about what you obviously have to do. Disagreeing with this advice automatically makes you a neophyte.

Common phraseology of bypass capacitor lore includes:
– You must use a mixture of low and high value capacitors to filter low and high frequency transients.
– You must use a tantalum bulk capacitor
– Sprinkling 1uF or 100nF caps around a board is stupid
and I’ve not made this one up:
– If you don’t know how to properly design capacitor bypassing, you should not be an EE.
[Of course, by “proper” they mean follow their advice]

I’ve been told by other reputable sources that since good MLCC [multi-layer ceramic capacitors] of high value and good electrolyte are now available, that most of these rules are exaggerated as yet another way for some engineers to claim superiority over others.

I decided to perform a few simple measurements to help me figure out for myself what I need to do when designing a circuit with bypass capacitors. Feel free to post below and offer advice as to how I’m wrong and/or what I should do with my graphs.

Test setup:
I have a simple “DG8SAQ” Vector Network Analyzer that I bought from SDR-Kits. It’s a reasonably good value and covers the range of 1kHz to 1.3 GHz. Without any fancy impedance converters, I decided that using this 50-ohm system to measure capacitor impedance would not be an unreasonable analog to what is happening when a capacitor is used for bypassing.

Bypassing for high speed digital systems is demanding. Edge slew rates can easily reach into the GHz range for FPGA designs. Even common LVCMOS digital logic can be extremely demanding – a recent comparator I used (MAX962) will drive it’s output high/low in 2.3ns (specified at 5v. It will be somewhat slower at 3.3V)

What I decided to do is solder a couple SMA connectors adjacent to each other, as in the following picture:
2014-05-27 14.23.57

I calibrated VNA and soldered a few surface mount capacitors into the open space. I used the following values:
1 nF
10 nF
100 nF
1 uF

From basic theory we know that the impedance of a capacitor is, as written in Laplace domain:
1/(sC)

Where
s = j*W [complex frequency]
and
C = capacitance value in Farads

In reality, capacitors have ESR and ESL. ESR is equivalent series resistance, and ESL is equivalent series inductance.
Alternating current by definition makes the impedance of a capacitor change.
LCR

My measurement system is not perfect for at least one reason; the ESR of a capacitor is usually << 1 ohm. My VNA is a 50 ohm system. I cannot effectively measure the ESR with this system. These plots will reflect the ESL, which I can measure.

Firstly I measured a 1nF capacitor. This plot is the magnitude of the signal that goes through the capacitor. This is called “S21”
I measured from 10kHz to 100 MHz because this seems to be a range most people would be interested in:

[click image for larger version]
1nf_cap_impedanceNext I tested a 10nF capacitor of the same size and type:

10nf_cap_impedanceLooks pretty nice to me.

Now for the 100nF cap:

100nf_cap_impedance
I continued on with a 1uF capacitor. The plot is quite boring:

1uf_cap_impedanceIf you’ll notice: these last two plots went all the way up to 300 MHz. I thought there must be something interesting going on at some point. Not really.

My conclusions are based on the measurements that I’ve done. Obviously I have not included PCB parasitics in my test setup.
My conclusion is that for point-of-load bypass capacitors, the actual value of the capacitor makes little difference. I would not hesitate to use 100nF MLC-capacitors all over my PCB. Ideally the capacitors are placed as close to the power pins of the integrated circuits as possible, in order to make the current loops as small as possible.

Bypassing requirements for real circuits are very complicated. If you just have a fundamental sine wave current, you just pick one capacitor and be done with it.

I believe what I’ve shown is that the Fourier components of your load current that exceed about 1 MHz are easily handled by 100nF MLC capacitors, and that your lower frequency bypassing can be handled by a bulk capacitor that is located elsewhere on the board. Of course this depends on the inductance of your PCB traces.

Your system probably has intermittent loads switching on and off, or perhaps you’re building a switching power supply. The best bypassing setup would be an ideal capacitor of arbitrarily large capacitance value. This would theoretically cover your Fourier components from a few Hertz up to hundreds of MHz. Recently I’ve been using MLCC as large as 100uF with the X5R rated dielectric (never use Y5V!) I believe these new enormous MLCC are nearly ideal capacitors. They are expensive but I highly recommend them, especially if your alternative is a tantalum capacitor.

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3 Comments

  1. One should be careful when bypassing digital IC’s ans they can consume a lot of current on the clock edges.. I have heard about processor IC’s needing 50 to 100 Amps on the edges so in this case you would want large low esr caps. For a lot of other things bypassing is not terribly important.

  2. Hi Martin,

    I think you have made a wrong conclusion. The measurements are correct but misleading. You measure the transition loss but this is not what characterize the capacitor, the capacitor is characterized by its capacitance, in case of supply decoupling this is the ability to deliver current under demand. Every capacitor has a self resonance point, the exact frequncy depend on type, size, ceramics, capacitance, etc. Check the datasheets of Murata or AVX and you will see the plots. After the resonance point the capacitor is actually a lossy inductor it will just alter the phase but is not able to deliver current. The suggested value of 100nf is almost always good for almost all aplications. Sometimes you may need a bigger cap just because you circuit need more current or a combination smaller cap and bigger cap both in the nf range because you need that current to be delivered faster. There are 2 important things to consider – how fast is the edge of the signal and what is the load. Logically – infinitely short front or infinitely big load will require infinite amount of current to be delivered during level change. You are discussing the MLCC caps, you are right – they are very good, still not perfect. They also have a temperature coefficient which you may need to consider, after certain temperature they can loose a lot of capacitance. I would not say that tantalum caps are worse or better – they are just different. Some values, usually the smaller ones, can be replaced by ceramics. The bigger values are not practical because of the price. Every case is different and this is why it is called engineering job 🙂 rule of thumb is not really an engineering method.
    Regarding the DG8SAQ – I think this is wrongly advertised as a vector network analyser. I see just one input, so you have just one detector. That mean you can measure only transmission or reflection but not both. To measure the reflection you need a bridge. If you want to measure the impedance of those caps you need an equipment which can measure both transmission and reflection simultaneously toghether with phase or real vector network analyser – http://www.rohde-schwarz.com/en/product/znb-productstartpage_63493-11648.html . Such measurement can characterize the real nature of the component.

    All the best,
    Velkov

  3. Thank you for writing such a detailed reply.

    I was measuring the impedance of various capacitors vs. frequency. My understanding is that the SRF will occur at some point, after which the inductance of the capacitor will begin to dominate.

    My assertion was challenging the age-old design technique (or arbitrary guideline) which many people claim to be true; “you must put smaller value capacitors nearer the point of load because they have better high frequency response”

    I believe I have proved this to not be true. I am well aware that you need a certain number of Farads of capacitance to prevent voltage from dropping during a discrete charge transition such as if half of your FPGA pins are switching simultaneously.

    The DG8SAQ only measures one direction at a time. You must flip the DUT around to measure the opposing S-parameters. I neglected to flip my capacitors around. If you would like to lend me a Rohde Schwarz VNA I will repeat my test more thoroughly 😉

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